1. Field of the Invention
The present invention relates to the field of random number generators, and more specifically to random number generators in the form of bit flows originating from one or several noise sources, digital or digitized.
2. Discussion of the Related Art
FIG. 1 very schematically shows in the form of blocks an example of a bit flow generator of the type to which the present invention applies.
Such a generator is based on the use of a noise source 1 (NS) providing an analog noise to an analog-to-digital conversion element 2 (CAD) clocked by a clock CLK and providing a bit flow BS. Source 1 is, for example, formed of one or several oscillators having their outputs added up to provide an analog noise at the input of converter 2. Converter 2 may, in simplified fashion, be a comparator associated with a flip-flop.
The quality of a random generator or more generally of a noise source is measured by the quality of its random character, that is, the equiprobability for flow BS to provide any number and, in particular, the equiprobability of finding 0s and 1s in the flow.
In practice, there are risks for flow BS provided by converter 2 not to have an equiprobable distribution of its elements (bits or bit words). In particular, noise source 1 generally uses oscillators for which there is a risk of synchronization, together or with clock CLK. In case of a synchronization, the output state (flow BS) remains constant.
To improve the equiprobability of a bit flow supposed to be random, flow BS crosses a normalization circuit 3 (NORM) providing a modified bit train NBS and in which the equiprobable character of the zeros and ones in the flow is improved.
FIG. 2 shows a conventional example of a circuit 3 for normalizing a bit flow BS applying a so-called Von Neumann method. Such a circuit 3 is based on an analysis of incoming bit flow BS, by bit pairs. A storage element 4 (BUFF) enabling processing of the bits, by pairs, in a state determination circuit 5 which provides normalized bit flow NBS, is then used. According to the Von Neumann method, if the bit pair is 10, a state 1 is generated. If the bit pair is 01, a state 0 is generated. If the bit pair is 00 or 11, it is ignored, that is, no state is output.
A disadvantage of the Von Neumann method is that the rate of normalized bit flow NBS is not constant, that is, the period with which the bits are provided is not regular. In a simple Von Neumann circuit such as described hereabove, the bit rate of flow NBS varies between twice and four times less than the rate of input flow BS.